diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index d88124a..bfbf3a8 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -248,7 +248,7 @@
 #endif
 
 #ifdef CONFIG_POST
-u #define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DIAG
 #endif
 
 /*
diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h
index 2191c7b..46edd08 100644
--- a/include/configs/LANTEC.h
+++ b/include/configs/LANTEC.h
@@ -106,6 +106,7 @@
 #undef CONFIG_CMD_IRQ
 #undef CONFIG_CMD_JFFS2
 #undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MFSL
 #undef CONFIG_CMD_MII
 #undef CONFIG_CMD_MMC
 #undef CONFIG_CMD_NAND
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index f3e5330..713518d 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -227,6 +227,7 @@
 #undef CONFIG_CMD_HWFLOW
 #undef CONFIG_CMD_IDE
 #undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MFSL
 #undef CONFIG_CMD_MMC
 #undef CONFIG_CMD_NAND
 #undef CONFIG_CMD_PCMCIA
@@ -405,9 +406,9 @@
 #define CFG_BCR			0x100C0000
 #define CFG_SIUMCR		0x0A200000
 #define CFG_SCCR		SCCR_DFBRG01
-#define CFG_BR0_PRELIM		CFG_FLASH_BASE | 0x00001801
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001801)
 #define CFG_OR0_PRELIM		0xFF800876
-#define CFG_BR1_PRELIM		CFG_BCSR | 0x00001801
+#define CFG_BR1_PRELIM		(CFG_BCSR | 0x00001801)
 #define CFG_OR1_PRELIM		0xFFFF8010
 
 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 3a6c977..14b041e 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -165,6 +165,7 @@
 #undef CONFIG_CMD_IDE
 #undef CONFIG_CMD_JFFS2
 #undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MFSL
 #undef CONFIG_CMD_MMC
 #undef CONFIG_CMD_NAND
 #undef CONFIG_CMD_PCMCIA
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 45a7d81..81db96f 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -265,7 +265,7 @@
 #define CONFIG_I2C_CMD_TREE
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{{0,0x69}} /* Don't probe these addrs */
 #define CFG_I2C_OFFSET		0x3000
 #define CFG_I2C2_OFFSET		0x3100
 
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index 5e12dab..2f6de81 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -119,6 +119,7 @@
 #undef CONFIG_CMD_IRQ
 #undef CONFIG_CMD_JFFS2
 #undef CONFIG_CMD_MII
+#undef CONFIG_CMD_MFSL
 #undef CONFIG_CMD_MMC
 #undef CONFIG_CMD_NAND
 #undef CONFIG_CMD_PCI
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index f412ec8..025c249 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -321,6 +321,7 @@
 #undef CONFIG_CMD_JFFS2
 #undef CONFIG_CMD_KGDB
 #undef CONFIG_CMD_MII
+#undef CONFIG_CMD_MFSL
 #undef CONFIG_CMD_MMC
 #undef CONFIG_CMD_NAND
 #undef CONFIG_CMD_PCI
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index 79e6aa1..ff57240 100644
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -294,7 +294,7 @@
 #define CONFIG_BOOTP_BOOTPATH
 
 #define CONFIG_BOOTP_BOOTFILESIZE
-#definef CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS
 
 /* undef this to save memory */
 #define CFG_LONGHELP
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
index b789067..2f64ec2 100644
--- a/include/configs/hymod.h
+++ b/include/configs/hymod.h
@@ -199,6 +199,7 @@
 #undef CONFIG_CMD_IDE
 #undef CONFIG_CMD_JFFS2
 #undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_MFSL
 #undef CONFIG_CMD_MMC
 #undef CONFIG_CMD_PCMCIA
 #undef CONFIG_CMD_PCI
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
index 4237228..f4f33f3 100644
--- a/include/configs/mpc7448hpc2.h
+++ b/include/configs/mpc7448hpc2.h
@@ -375,9 +375,9 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1/* Flash can be at one of two addresses */
+#define CFG_MAX_FLASH_BANKS	1		/* Flash can be at one of two addresses */
 #define FLASH_BANK_SIZE		0x01000000	/* 16 MB Total */
-#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, /* CFG_FLASH_BASE2 */ }
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index 6e451d8..fe7de7b 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -25,29 +25,30 @@
 /*
  * Debug
  *
- * DEBUG			- Define this is you want extra debug info
- * GTREGREAD			- Required to build with debug
- * do_bdinfo			- Required to build with debug
+ * DEBUG		- Define this is you want extra debug info
+ * GTREGREAD		- Required to build with debug
+ * do_bdinfo		- Required to build with debug
  */
 
 #undef	DEBUG
-#define	GTREGREAD(x)			0xFFFFFFFF
+#ifdef	DEBUG
+#define	GTREGREAD(x)	0xFFFFFFFF
 #define	do_bdinfo(a,b,c,d)
-
+#endif
 
 /*
  * CPU type
  *
- * CONFIG_7xx			- We have a 750 or 755 CPU
- * CONFIG_74xx			- We have a 7400 CPU
- * CONFIG_ALTIVEC		- We have altivec enabled CPU (only 7400)
- * CONFIG_BUS_CLK		- System bus clock in Hz
+ * CONFIG_7xx		- We have a 750 or 755 CPU
+ * CONFIG_74xx		- We have a 7400 CPU
+ * CONFIG_ALTIVEC	- We have altivec enabled CPU (only 7400)
+ * CONFIG_BUS_CLK	- System bus clock in Hz
  */
 
 #define	CONFIG_7xx
 #undef	CONFIG_74xx
 #undef	CONFIG_ALTIVEC
-#define CONFIG_BUS_CLK			66000000
+#define CONFIG_BUS_CLK	66000000
 
 
 /*
@@ -97,18 +98,18 @@
  * Serial configuration
  *
  * CONFIG_CONS_INDEX		- Serial console port number (COM1)
- * CONFIG_BAUDRATE			- Serial speed
+ * CONFIG_BAUDRATE		- Serial speed
  */
 
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_BAUDRATE			9600
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
 
 
 /*
  * PCI config
  *
- * CONFIG_PCI				- Enable PCI bus
- * CONFIG_PCI_PNP			- Enable Plug & Play support
+ * CONFIG_PCI			- Enable PCI bus
+ * CONFIG_PCI_PNP		- Enable Plug & Play support
  * CONFIG_PCI_SCAN_SHOW		- Enable display of devices at startup
  */
 
@@ -120,9 +121,9 @@
 /*
  * Network config
  *
- * CONFIG_NET_MULTI			- Support for multiple network interfaces
- * CONFIG_EEPRO100			- Intel 8255x Ethernet Controller
- * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
+ * CONFIG_NET_MULTI		- Support for multiple network interfaces
+ * CONFIG_EEPRO100		- Intel 8255x Ethernet Controller
+ * CONFIG_EEPRO100_SROM_WRITE	- Enable writing to network card ROM
  */
 
 #define	CONFIG_NET_MULTI
@@ -145,7 +146,7 @@
  * Boot config
  *
  * CONFIG_BOOTCOMMAND		- Command(s) to execute to auto-boot
- * CONFIG_BOOTDELAY			- How long to wait before auto-boot (in sec)
+ * CONFIG_BOOTDELAY		- How long to wait before auto-boot (in sec)
  */
 
 #define CONFIG_BOOTCOMMAND		\
@@ -169,79 +170,79 @@
  *
  * This board runs in a standard CHRP (Map-B) configuration.
  *
- *	Type		Start		End			Size	Width	Chip Sel
+ *	Type	    Start	End	    Size    Width   Chip Sel
  *	----------- ----------- ----------- ------- ------- --------
- *	SDRAM		0x00000000	0x04000000	64MB	64b		SDRAMCS0
- *	User LED's	0x78000000						RCS3
- *	UART		0x7C000000						RCS2
- *	Mailbox		0xFF000000						RCS1
- *	Flash		0xFFC00000	0xFFFFFFFF	4MB	64b		RCS0
+ *	SDRAM	    0x00000000	0x04000000  64MB    64b	    SDRAMCS0
+ *	User LED's  0x78000000				    RCS3
+ *	UART	    0x7C000000				    RCS2
+ *	Mailbox	    0xFF000000				    RCS1
+ *	Flash	    0xFFC00000	0xFFFFFFFF   4MB    64b	    RCS0
  *
  * Flash sectors are laid out as follows.
  *
- *	Sector	Start		End			Size	Comments
+ *	Sector	Start		End	Size	Comments
  *	------- ----------- ----------- ------- -----------
- *	 0		0xFFC00000	0xFFC3FFFF	256KB
- *   1		0xFFC40000	0xFFC7FFFF	256KB
- *	 2		0xFFC80000	0xFFCBFFFF	256KB
- *	 3		0xFFCC0000	0xFFCFFFFF	256KB
- *	 4		0xFFD00000	0xFFD3FFFF	256KB
- *	 5		0xFFD40000	0xFFD7FFFF	256KB
- *	 6		0xFFD80000	0xFFDBFFFF	256KB
- *	 7		0xFFDC0000	0xFFDFFFFF	256KB
- *   8		0xFFE00000	0xFFE3FFFF	256KB
- *	 9		0xFFE40000	0xFFE7FFFF	256KB
- *  10		0xFFE80000	0xFFEBFFFF	256KB
- *  11		0xFFEC0000	0xFFEFFFFF	256KB
- *  12		0xFFF00000	0xFFF3FFFF	256KB	U-Boot code here
- *  13		0xFFF40000	0xFFF7FFFF	256KB
- *  14		0xFFF80000	0xFFFBFFFF	256KB
- *  15		0xFFFC0000	0xFFFDFFFF	128KB
- *  16		0xFFFE0000	0xFFFE7FFF	 32KB	U-Boot env vars here
- *  17		0xFFFE8000	0xFFFEFFFF	 32KB	U-Boot backup copy of env vars here
- *  18		0xFFFF0000	0xFFFFFFFF	 64KB
+ *	 0	0xFFC00000  0xFFC3FFFF	256KB
+ *	 1	0xFFC40000  0xFFC7FFFF	256KB
+ *	 2	0xFFC80000  0xFFCBFFFF	256KB
+ *	 3	0xFFCC0000  0xFFCFFFFF	256KB
+ *	 4	0xFFD00000  0xFFD3FFFF	256KB
+ *	 5	0xFFD40000  0xFFD7FFFF	256KB
+ *	 6	0xFFD80000  0xFFDBFFFF	256KB
+ *	 7	0xFFDC0000  0xFFDFFFFF	256KB
+ *	 8	0xFFE00000  0xFFE3FFFF	256KB
+ *	 9	0xFFE40000  0xFFE7FFFF	256KB
+ *	10	0xFFE80000  0xFFEBFFFF	256KB
+ *	11	0xFFEC0000  0xFFEFFFFF	256KB
+ *	12	0xFFF00000  0xFFF3FFFF	256KB	U-Boot code here
+ *	13	0xFFF40000  0xFFF7FFFF	256KB
+ *	14	0xFFF80000  0xFFFBFFFF	256KB
+ *	15	0xFFFC0000  0xFFFDFFFF	128KB
+ *	16	0xFFFE0000  0xFFFE7FFF	 32KB	U-Boot env vars here
+ *	17	0xFFFE8000  0xFFFEFFFF	 32KB	U-Boot backup copy of env vars here
+ *	18	0xFFFF0000  0xFFFFFFFF	 64KB
  */
 
 
 /*
  * SDRAM config - see memory map details above.
  *
- * CFG_SDRAM_BASE			- Start address of SDRAM, this _must_ be zero!
- * CFG_SDRAM_SIZE			- Total size of contiguous SDRAM bank(s)
+ * CFG_SDRAM_BASE		- Start address of SDRAM, this _must_ be zero!
+ * CFG_SDRAM_SIZE		- Total size of contiguous SDRAM bank(s)
  */
 
-#define CFG_SDRAM_BASE			0x00000000
-#define CFG_SDRAM_SIZE			0x04000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		0x04000000
 
 
 /*
  * Flash config - see memory map details above.
  *
- * CFG_FLASH_BASE			- Start address of flash memory
- * CFG_FLASH_SIZE			- Total size of contiguous flash mem
+ * CFG_FLASH_BASE		- Start address of flash memory
+ * CFG_FLASH_SIZE		- Total size of contiguous flash mem
  * CFG_FLASH_ERASE_TOUT		- Erase timeout in ms
  * CFG_FLASH_WRITE_TOUT		- Write timeout in ms
  * CFG_MAX_FLASH_BANKS		- Number of banks of flash on board
  * CFG_MAX_FLASH_SECT		- Number of sectors in a bank
  */
 
-#define CFG_FLASH_BASE			0xFFC00000
-#define CFG_FLASH_SIZE			0x00400000
+#define CFG_FLASH_BASE		0xFFC00000
+#define CFG_FLASH_SIZE		0x00400000
 #define CFG_FLASH_ERASE_TOUT	250000
 #define CFG_FLASH_WRITE_TOUT	5000
-#define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		19
+#define CFG_MAX_FLASH_BANKS	1
+#define CFG_MAX_FLASH_SECT	19
 
 
 /*
  * Monitor config - see memory map details above
  *
- * CFG_MONITOR_BASE			- Base address of monitor code
- * CFG_MALLOC_LEN			- Size of malloc pool (128KB)
+ * CFG_MONITOR_BASE		- Base address of monitor code
+ * CFG_MALLOC_LEN		- Size of malloc pool (128KB)
  */
 
-#define CFG_MONITOR_BASE		TEXT_BASE
-#define CFG_MALLOC_LEN			0x20000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_LEN		0x20000
 
 
 /*
@@ -259,16 +260,16 @@
  * CFG_PROMPT			- Prompt string
  */
 
-#define CFG_BARGSIZE			1024
-#define CFG_BOOTMAPSZ			0x800000
-#define CFG_CBSIZE			1024
-#define CFG_LOAD_ADDR			0x100000
+#define CFG_BARGSIZE		1024
+#define CFG_BOOTMAPSZ		0x800000
+#define CFG_CBSIZE		1024
+#define CFG_LOAD_ADDR		0x100000
 #define CFG_LONGHELP
-#define CFG_MAXARGS			16
-#define CFG_MEMTEST_START		0x00040000
-#define CFG_MEMTEST_END			0x00040100
-#define CFG_PBSIZE			1024
-#define CFG_PROMPT			"=> "
+#define CFG_MAXARGS		16
+#define CFG_MEMTEST_START	0x00040000
+#define CFG_MEMTEST_END		0x00040100
+#define CFG_PBSIZE		1024
+#define CFG_PROMPT		"=> "
 
 
 /*
@@ -280,12 +281,12 @@
  * CFG_ENV_SECT_SIZE		- Size of sector containing env vars (32KB)
  */
 
-#define CFG_ENV_IS_IN_FLASH		1
-#define CFG_ENV_ADDR			0xFFFE0000
-#define CFG_ENV_SIZE			0x1000
-#define CFG_ENV_ADDR_REDUND		0xFFFE8000
-#define CFG_ENV_SIZE_REDUND		0x1000
-#define CFG_ENV_SECT_SIZE		0x8000
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0xFFFE0000
+#define CFG_ENV_SIZE		0x1000
+#define CFG_ENV_ADDR_REDUND	0xFFFE8000
+#define CFG_ENV_SIZE_REDUND	0x1000
+#define CFG_ENV_SECT_SIZE	0x8000
 
 
 /*
@@ -296,15 +297,15 @@
  * copied to top of RAM by the init code.
  *
  * CFG_INIT_RAM_ADDR		- Address of Init RAM, above exception vect
- * CFG_INIT_RAM_END			- Size of Init RAM
+ * CFG_INIT_RAM_END		- Size of Init RAM
  * CFG_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
  * CFG_GBL_DATA_OFFSET		- Start of global data, top of stack
  */
 
-#define CFG_INIT_RAM_ADDR		(CFG_SDRAM_BASE + 0x4000)
-#define CFG_INIT_RAM_END		0x4000
-#define CFG_GBL_DATA_SIZE		128
-#define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + 0x4000)
+#define CFG_INIT_RAM_END	0x4000
+#define CFG_GBL_DATA_SIZE	128
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 
 
 /*
@@ -341,71 +342,71 @@
  * Cache config
  *
  * CFG_CACHELINE_SIZE		- Size of a cache line (CPU specific)
- * CFG_L2					- L2 cache enabled if defined
- * L2_INIT					- L2 cache init flags
- * L2_ENABLE				- L2 cache enable flags
+ * CFG_L2			- L2 cache enabled if defined
+ * L2_INIT			- L2 cache init flags
+ * L2_ENABLE			- L2 cache enable flags
  */
 
-#define CFG_CACHELINE_SIZE		32
+#define CFG_CACHELINE_SIZE	32
 #undef	CFG_L2
-#define L2_INIT					0
-#define L2_ENABLE				0
+#define L2_INIT			0
+#define L2_ENABLE		0
 
 
 /*
  * Clocks config
  *
- * CFG_BUS_HZ				- Bus clock frequency in Hz
- * CFG_BUS_CLK				- As above (?)
- * CFG_HZ					- Decrementer freq in Hz
+ * CFG_BUS_HZ			- Bus clock frequency in Hz
+ * CFG_BUS_CLK			- As above (?)
+ * CFG_HZ			- Decrementer freq in Hz
  */
 
-#define CFG_BUS_HZ				CONFIG_BUS_CLK
-#define CFG_BUS_CLK				CONFIG_BUS_CLK
-#define CFG_HZ					1000
+#define CFG_BUS_HZ		CONFIG_BUS_CLK
+#define CFG_BUS_CLK		CONFIG_BUS_CLK
+#define CFG_HZ			1000
 
 
 /*
  * Serial port config
  *
  * CFG_BAUDRATE_TABLE		- List of valid baud rates
- * CFG_NS16550				- Include the NS16550 driver
+ * CFG_NS16550			- Include the NS16550 driver
  * CFG_NS16550_SERIAL		- Include the serial (wrapper) driver
- * CFG_NS16550_CLK			- Frequency of reference clock
+ * CFG_NS16550_CLK		- Frequency of reference clock
  * CFG_NS16550_REG_SIZE		- 64-bit accesses to 8-bit port
- * CFG_NS16550_COM1			- Base address of 1st serial port
+ * CFG_NS16550_COM1		- Base address of 1st serial port
  */
 
-#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 #define CFG_NS16550
 #define CFG_NS16550_SERIAL
-#define CFG_NS16550_CLK			3686400
+#define CFG_NS16550_CLK		3686400
 #define CFG_NS16550_REG_SIZE	-8
-#define CFG_NS16550_COM1		0x7C000000
+#define CFG_NS16550_COM1	0x7C000000
 
 
 /*
  * PCI Config - Address Map B (CHRP)
  */
 
-#define CFG_PCI_MEMORY_BUS      0x00000000
-#define CFG_PCI_MEMORY_PHYS     0x00000000
-#define CFG_PCI_MEMORY_SIZE     0x40000000
-#define CFG_PCI_MEM_BUS         0x80000000
-#define CFG_PCI_MEM_PHYS        0x80000000
-#define CFG_PCI_MEM_SIZE        0x7D000000
-#define CFG_ISA_MEM_BUS         0x00000000
-#define CFG_ISA_MEM_PHYS        0xFD000000
-#define CFG_ISA_MEM_SIZE        0x01000000
-#define CFG_PCI_IO_BUS          0x00800000
-#define CFG_PCI_IO_PHYS         0xFE800000
-#define CFG_PCI_IO_SIZE         0x00400000
-#define CFG_ISA_IO_BUS          0x00000000
-#define CFG_ISA_IO_PHYS         0xFE000000
-#define CFG_ISA_IO_SIZE         0x00800000
+#define CFG_PCI_MEMORY_BUS	0x00000000
+#define CFG_PCI_MEMORY_PHYS	0x00000000
+#define CFG_PCI_MEMORY_SIZE	0x40000000
+#define CFG_PCI_MEM_BUS		0x80000000
+#define CFG_PCI_MEM_PHYS	0x80000000
+#define CFG_PCI_MEM_SIZE	0x7D000000
+#define CFG_ISA_MEM_BUS		0x00000000
+#define CFG_ISA_MEM_PHYS	0xFD000000
+#define CFG_ISA_MEM_SIZE	0x01000000
+#define CFG_PCI_IO_BUS		0x00800000
+#define CFG_PCI_IO_PHYS		0xFE800000
+#define CFG_PCI_IO_SIZE		0x00400000
+#define CFG_ISA_IO_BUS		0x00000000
+#define CFG_ISA_IO_PHYS		0xFE000000
+#define CFG_ISA_IO_SIZE		0x00800000
 #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
-#define CFG_ISA_IO              CFG_ISA_IO_PHYS
-#define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS
+#define CFG_ISA_IO		CFG_ISA_IO_PHYS
+#define CFG_60X_PCI_IO_OFFSET	CFG_ISA_IO_PHYS
 
 
 /*
@@ -420,12 +421,12 @@
 /*
  * Boot flags
  *
- * BOOTFLAG_COLD			- Indicates a power-on boot
- * BOOTFLAG_WARM			- Indicates a software reset
+ * BOOTFLAG_COLD		- Indicates a power-on boot
+ * BOOTFLAG_WARM		- Indicates a software reset
  */
 
-#define BOOTFLAG_COLD			0x01
-#define BOOTFLAG_WARM			0x02
+#define BOOTFLAG_COLD		0x01
+#define BOOTFLAG_WARM		0x02
 
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 83a81fe..1831bef 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -328,7 +328,7 @@
 #define CONFIG_I2C_CMD_TREE
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
 #define CFG_I2C1_OFFSET		0x3000
 #define CFG_I2C2_OFFSET		0x3100
 #define CFG_I2C_OFFSET		CFG_I2C2_OFFSET